Metal interconnect structures are an important part of VLSI integrated circuits. The metal interconnect structures typically include metal lines and vias. The vias are used to interconnect the metal lines with conductive structures above and below the metal interconnect layer. Sophisticated ICs may include several layers of metal interconnect structures. The metal lines are commonly used on VLSI integrated circuits for carrying digital signals, analogs signals, or bias power to and from the embedded semiconductor devices.
Metal interconnects on different levels and on the same level must be electrically isolated from one another to avoid short circuits. Typically, after metal lines have been formed through metal etching, a dielectric layer is deposited over the metal lines for insulation purposes. This dielectric layer is referred to as either an intermetal dielectric (IMD), or an interlayer dielectric (ILD). The insulating dielectric layer typically is formed from a composite of multiple layers of oxide. For example, in many processes, the insulative dielectric layer comprises a bulk oxide layer followed by a cap oxide layer.
As the aspect ratios of the gaps between metal lines increases, it has been found that conventional chemical vapor deposition of oxides oftentimes fail to exhibit acceptable gap filling characteristics. Imperfections and discontinuities such as keyholes and incomplete filling occur.
One type of oxide that has demonstrated encouraging gap filling capabilities is the high density plasma chemical vapor deposition (HDPCVD) oxide. HDPCVD oxide technology has only been recently developed in the past few years. Thus, HDPCVD oxide remains a promising gap filling alternative for high aspect ratio gaps.
Another important consideration when forming an IMD or ILD is the planarity of the top surface of the oxide. For a multitude of reasons, it is important that the IMD have a planar surface. Because of the topography of the metal interconnect structure, it is sometimes difficult to achieve a planar oxide surface with HDPCVD oxides. Further, because of the particular characteristics of HDPCVD oxide, it has been found that triangular peaks are formed on the top of metal lines. This can be seen in FIG. 1, where exemplary metal lines 101 are formed atop of a substrate. A layer of HDPCVD oxide 103 is deposited over the metal lines 101. Unfortunately, during the deposition prosess, triangular peaks 105 are formed atop the metal lines 101.
Because of the triangular peaks 105, a subsequently deposited plasma enhanced (PE) oxide layer 107 has variations in its topography. The topography of the cap PE oxide layer 107 is very sensitive to the topography of the underlying layer. If the peaks 105 have a positive curvature (i.e., convex to the surface), then the cap oxide layer 107 will form a "keyhole" 109. However, if the curvature can be made negative (i.e. concave to the surface), then the cap oxide layer 107 will be a smoother topography with less step height. With a lower step height, less further processing of the PE oxide layer 107 through a chemical mechanical polishing (CMP) process is necessary.
If the HDPCVD oxide layer 105 could be deposited in such a manner so as to reduce the triangular peaks 105 and to make them concave, then the variation in topography of the PE oxide layer 107 may be reduced, thereby reducing the amount of CMP required (and also the thickness of the PE oxide layer 107). This would improve cost and throughput during the manufacturing process.